The present invention generally relates to a programmable logic array, and more particularly to a reduction in power consumed in a programmable logic array.
As is well known, a programmable logic array (hereafter simply referred to as a PLA) is a circuit in which a desired logical function can be programed. A PLA has such a structure that circuit elements are regularly arranged as conventional memories.
A conventional PLA is described with reference to FIGS. 1 and 2. Referring to these figures, a PLA 1 includes an OR array and an AND array, each of which includes precharge transistors and discharge transistors. A clock signal CLK as shown in FIG. 2(A) is applied to the PLA 1. When the clock signal CLK is held at a high level (hereafter simply referred to H level), the PLA 1 is precharged. On the other hand, when the clock signal CLK is held at a low level (hereafter simply referred to as L level), the PLA 1 is discharged. Therefore, the state of the PLA changes as shown in FIG. 2(B) where "Pre" indicates a precharged state, and "Dis" indicates a discharged state.
The PLA 1 enters data supplied to an input data terminal IN thereof in the precharged state, and outputs a logic output to a latch circuit 2 in the discharged state. An AND gate 3 makes an AND operation on an inverted clock pulse signal CLK and a read signal RD as shown in FIG. 2(C), and generates a control signal. The latch circuit 2 latches a logic output from the PLA 1 at the rise of the inverted clock pulse signal CLK. Therefore, the output signal of the latch circuit 2 changes with a timing as shown in FIG. 2(D).
As is illustrated in FIG. 2(B), the precharging and discharging are alternately carried out all the time. This means that the PLA 1 is always accessed, or in other words, the PLA 1 is accessed during a time even when it is not required to read data from the PLA 1. The above-mentioned access operation is wasteful of power, since current passes through discharge transistors during discharge periods even when the PLA 1 is not accessed. Recently, PLAs are fabricated as large scale integrated circuits. Therefore, it is particularly desired that power consumption is as low as possible.
In view of reduction of power consumed in PLAs, an improvement in configuration of PLAs has been proposed (see Japanese Laid-Open Patent Application Nos. 52-137228, 52-137229 and 59-208944). In the proposed improvement, a PLA is divided into a plurality of blocks (sub-PLAs). A divided block to be selected is supplied with power, and the remaining blocks (which are not selected) are supplied with no power. For this purpose, ON/OFF switches are interposed between a power source line and the divided blocks of the PLA. In the alternative, a divided block of an OR array which is not selected at present, is inhibited from being precharged.
However, as will be described later, problems occur by simply turning the power source OFF. Additionally, when the block of the OR array which is not currently selected, is selected, the selected block must be subjected to the precharging operation. This leads to a decrease of operation speed.